Signal Level Hardware in the Loop Test Platform for MVDC Power Systems

  Copyright: © RWTH Aachen

Hardware in the loop simulations are today widely accepted as the step between simulation environment and field tests. To identify potential issues which could appear in a Power Hardware in the Loop Simulation a control hardware in the loop simulation is often performed.

DC Microgrids are becoming a meaningful solution in diffe- rent cases, particularly given the diffusion of power electro- nic interfaces for load and generation. Until now, one of the main issues of these grids has been stability, challenged by the constant power loads. Typically, the stabilization of the DC bus is performed through the control of the load side converters. In the project Advanced Method for Robust Sta- bility we have demonstrated that, as in the classical power system, the generation can be controlled to follow the load, and therefore the control action to guarantee stability may be taken at the converters which supply the DC bus.

For addressing in a systematic way the challenge of genera- tion side control, a first step is the synthesis of the control algorithm based on the averaged model. The theory can then be verified with offline simulation. In a second step the implementation of the control algorithm should be tes- ted prior to deployment, in the hardware in the loop envi- ronment, under repeatable, controlled and specified bound- ary conditions. This yields additional verification instead of trying to implement the algorithm directly in the final hard- ware. Where we can observe a control performances that is nearer to the reality without having the restrictions of a predefined target architecture. To support this task, we have set up a signal in the loop test bed, where the actual control algorithms are tested under real time conditions.

The scheme of our test bed is shown in the picture. The al- gorithm is implemented in the development PC and then uploaded on either the real-time target or the FPGA, both capable to exchange data with the real-time environment that simulates the power section of the microgrid. Currently this simulation is performed in RTDS. But we are currently integrating our OPAL-RT unit for increasing our flexibility to easily include switching models of converter and of further components, which were originally modeled in MATLAB- Simulink.

The LabVIEW-FPGA combination can be operated in two modes. In the first mode LabVIEW uses the FPGA only for data acquisition from the real-time simulation environment. The control algorithm is executed through a standard PC hardware, which runs LabVIEW real-time target. In this scenario, the FPGA board receives the data from the ana- log and digital I/O port of RTDS, and hands them over to the LabVIEW real-time target via PCIe port. The execution of the digital control algorithm is performed on the real-time target. The effect of the additional data handover increases the time delay, which could pose an artificial restriction to high bandwidth, low latency algorithms.

In the second mode the control algorithm, originally im- plemented in LabVIEW, is downloaded on the FPGA, which, besides I/O functions, this time also executes the control code, and operates as a digital controller, as it can be found in common off the shelf converters, where the PWM is generated by FPGA which is much faster than a DSP. The time delay of the control loop on the FPGA is, significantly shorter than with the operation on the real- time target, as no data has to transferred over the PCIe bus and therefore we can achieve such better performance. This platform has been so far successfully tested with the three algorithms developed during the Advanced Method for Robust Stability Project.