FEN ESCape: Einheitliche Schutzarchitektur für DC-Netze auf System- und Komponentenebene
Team Advanced Control Methods for Power Systems and HiL
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A mature protection architecture for smart power grids of the future, in particular direct current (DC) grids, is the key to the broad acceptance and market penetration of these grids. Requirements based on application scenarios will be evaluated for the necessary protection architecture, and the individual protection components. In addition, the higher-level coordination of all components involved in protection will be adapted to these requirements. Furthermore, the individual faults must be automatically detected, localized and cleared. In turn, reliable protection components are required to clear the faults, depending on the requirements imposed by the grid used.
Einheitliche Schutzarchitektur für DC-Netze auf System- und Komponentenebene (ESCape) is a project funded by the Federal Ministry of Education and Research (BMBF) (FKZ03SF0595) within the scope of the Forschungscampus Flexible Elektrische Netze (FEN). The project started in 2020 and has a period of five years.
Work package of ACS: AP5 protection functions at a system level
Target of work package
This work package deals with the development of protection algorithms and strategies for DC or hybrid AC/DC systems. The project includes the analysis of the behavior of the systems during fault conditions. Algorithms and methods for fault detection, isolation and identification will be developed. Cases of arcing will also be analyzed. Furthermore, strategies for fault clearance, network restructuring, and restoration of normal operation will be developed. The work package also includes the development of protection algorithms to coordinate all protection components in the network. Additionally, security concerns regarding cyber-physical systems will be considered in the development of the aforementioned concepts. Based on all the results achieved so far, the algorithms will be implemented for DC networks and validated in hardware-in-the-loop (HiL) and real applications.